5.3.3. A940TWrapSM

In master mode, this block converts the ASB accesses from the core into pseudo-AHB accesses. This pseudo-AHB format is similar to AHB-Lite. The following sections of the code are explained:

Main state machine

The main state machine uses the state variable CurrentState (which is registered to create LastState). This can take the following enumerated values:

IDLE

Default state. Indicates that no transfer is taking place on the AHB. An IDLE cycle is indicated on HTRANSM.

LOCK_STALL

Start of SWP instruction. This state stalls the core to allow HLOCKM to be asserted for one cycle before commencing the read transaction. An IDLE cycle is indicated on HTRANSM.

READ_START

First cycle of a read transfer. A NONSEQ access is indicated on HTRANSM.

READ_BURST

Second and subsequent cycles of a 4-beat cache linefill. A SEQ access is indicated on HTRANSM.

READ_SEQ

Indicates sequential accesses in an undefined length burst of reads. A SEQ access is indicated on HTRANSM.

READ_BUSY

Indicates that the current undefined length burst of reads can continue. A BUSY cycle is indicated on HTRANSM.

READ_STALL

Indicates that the current undefined length burst of reads has been stalled but is to continue. A SEQ access is indicated on HTRANSM.

WRITE_START

First cycle of a write transfer. A NONSEQ access is indicated on HTRANSM.

WRITE_BURST

Second and subsequent cycles of a 4-beat write-buffer flush. A SEQ access is indicated on HTRANSM.

WRITE_BUSY

Indicates that the current undefined length burst of writes is to continue after the current access has completed. A BUSY cycle is indicated on HTRANSM.

WRITE_SEQ

Indicates sequential accesses in an undefined length burst of writes. A SEQ access is indicated on HTRANSM.

LAST_DATA

Allows the last access of a burst transfer to complete. An IDLE cycle is indicated on HTRANSM.

Figure 5.2 shows the possible state transitions. State transitions occur on the rising edge of HCLK. Transitions back to the same state can occur either when the access on the pseudo-AHB is waited, or during sequential accesses in a burst (WRITE_BURST and READ_BURST only). Those states that cannot transition back to themselves provide a single cycle to allow synchronization between events on the ASB and the AHB.

Figure 5.2. ARM940T AHB wrapper main state machine

Address generation

There are two internal sources of address:

  • a registered version of the core address

  • a locally incremented address created within A940TWrapSM.

The incremented address is used when sequential transfers on the AHB occur in the same cycle as on the ASB. At all other times, the registered version is used.

Wait states

Wait states on the AHB (indicated by HREADYM being LOW) are propagated to the ARM940T only when the core is attempting to access the bus. Because of this, a string of IDLE cycles on the ASB is not waited. Additional wait states (where one wait state equates to a single cycle of HCLK) are added as follows:

  • +1 at the start of each 4-beat cacheable or bufferable burst.

  • +1 for each beat of a burst write of undefined length. These are masked by wait states from the slave being accessed except for the final wait state at the end of the burst.

  • +1 for each beat of a burst read of undefined length. These are masked by wait states from the slave being accessed except for the initial wait state at the beginning of the burst.

  • +3 for a SWP instruction (comprising +2 for the read, +1 for the write).

Error support

The ARM940T AHB wrapper includes support for the ERROR response on HRESPM. The ERROR response is only valid for the following accesses:

  • read and write accesses to NCNB address regions

  • read accesses to NCB address regions.

Control signaling (HTRANSM, HSIZEM, HBURSTM, HPROTM)

Table 5.3 shows the control signal values used by the ARM940T AHB wrapper.

Table 5.3. Control signal values

Signal

Value

HTRANSM

00: IDLE

01: BUSY

10: NONSEQUENTIAL

11: SEQUENTIAL

HSIZEM

00: BYTE

01: HALFWORD

10: WORD

HBURSTM

001: INCR

011: INCR4

HPROTM

bit 3: 1 = cacheable, 0 = not cacheable (only valid for cache linefills, 0 for all other accesses)

bit 2: 1 = bufferable, 0 = not bufferable (only valid for 4-beat write buffer flushes, 0 for all other accesses)

bit 1: 1 = privileged access, 0 = user access

bit 0: 1 = data access, 0 = opcode fetch

Note

It is not possible within the AHB wrapper to fully determine the cacheable/bufferable properties of the memory area being accessed. Instead, the cacheable bit is set only when a 4-beat read is in progress (cache linefill), and the bufferable bit is set only when a 4-beat write is in progress (write buffer flush). Because of this, write buffer flushes which occur when there are less than three items in the buffer are not indicated as bufferable. Also, the lower bits of HPROTM (privileged/user and opcode/data) only become valid very late in the clock cycle. This is because they are derived through combinational logic from the BPROT outputs of the ARM940T core, that are themselves set after the falling edge of BCLK.

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