AHB CPU Wrappers Technical Reference Manual
Home > Introduction > CPU bus access wait states

1.2. CPU bus access wait states

The number of wait states added to CPU bus accesses by each of the CPU AHB wrappers is shown in Table 1.1.

Some wait states added by the AHB wrappers are unavoidable, but others can be masked by wait states from the slave which was accessed in the previous cycle. That is, if the previous access were to a zero-delay slave, the extra wait states added by the AHB wrapper are added to the number of cycles taken to complete the transaction. If the slave previously accessed asserted wait states, no extra cycles are required.

Table 1.1. CPU bus access wait states

CPU AHB wrapper

Added wait state

Reason

Comment

ARM7TDMI and ARM7TDMI-S

1

For each NONSEQ access from the core (except SWP accesses)

These are masked by wait states from the slave being accessed in the previous access cycle.

2

At the start of a SWP instruction

-

ARM720T

1

At the start of a SWP instruction

These are masked by wait states from the slave being accessed if a waited access immediately precedes the SWP.

ARM920T

1

For each access in a nonbuffered burst of writes (including single accesses, which appear as bursts of undefined length)

-

1

At the start of a SWP instruction

-

ARM940T

1

At the start of each cacheable/ bufferable burst

-

1

For each beat of a nonbuffered burst write

These are masked by wait states from the slave being accessed EXCEPT for the final wait state added at the end of the burst.

1

For each beat of a noncacheable burst read

These are masked by wait states from the slave being accessed EXCEPT for the initial wait state added at the beginning of the burst.

2

For the read access of a SWP instruction

-

1

For the write access of a SWP instruction

-

Copyright © 2001, 2003 ARM Limited. All rights reserved.ARM DDI 0169D
Non-Confidential
PDF file icon  PDF version
Home > Introduction > CPU bus access wait states