5.3.5. A940TWrapTest

The slave state machine uses the state variable NextState (which is registered to create CurrentState). This can take the following enumerated values:

MASTER_MODE

Default state, no TIC testing is taking place. The ARM940T core is granted the ASB bus through AGNT. In all other states, the core is degranted.

TEST_RESET

Entered on receiving the first access to the slave port. A counter keeps the state machine in TEST_RESET for eight cycles, during which time the ARM940T core is held in reset through BnRES. The AHB is waited through HREADYOUTS.

LAST_RESET

End of reset sequence. HREADYOUTS is deasserted to allow the first test access to continue.

Note

All ARM940T TIC vectors start with a write.

TEST_WRITE

A write access is occurring.

TURNAROUND

A turnaround cycle is required between a write access and a read access. The AHB is waited while this occurs.

TEST_READ

A read access is occurring.

TEST_IDLE1, 2, 3

These three states allow for a brief pause in the stream of test accesses to the core to occur without the core being regranted the ASB. If a read or write to the core is indicated during these states, the relevant state is entered and AGNT is not reasserted.

EXIT_TEST

Final test state before returning to MASTER_MODE.

Figure 5.3 shows the possible state transitions. State transitions occur on the rising edge of HCLK. Transitions back to the same state occur when the same type of access is to be performed again (either read, write, or no access).

Note

The ARM940T core always responds to slave accesses with zero wait states on the ASB.

Figure 5.3. ARM940T slave state machine

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