3.2.1. A7TWrap signals

This section describes the signal interface of A7TWrap. It does not describe the ARM7TDMI. Only those signals from the ARM7TDMI core that are used by the AHB wrapper are described. All other core signals must be connected to the external system in the same way as for a native core design. See the ARM7TDMI Datasheet for the relevant information.

Note

The exception is DOUT[31:0], which must be connected directly to the HWDATA[31:0] AHB bus and the DOUT[31:0] input on A7TWrap.

Table 3.1 describes the signals used by the ARM7TDMI AHB wrapper.

Table 3.1. ARM7TDMI AHB signal descriptions

Signal

Direction

Description

System inputs

HCLK

Input

Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.

HRESETn

Input

Reset. The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active LOW AHB signal.

Master inputs

HRDATAM[31:0]

Input

Read data bus. Used to transfer data to the ARM7TDMI in master mode.

HREADYM

Input

Transfer done. When HIGH, the HREADYM signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESPM[1:0]

Input

Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response.

HGRANTM

Input

Bus grant. Indicates that the ARM7TDMI is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADYM is HIGH, so a master gains access to the bus when both HREADYM and HGRANTM are HIGH.

Master outputs

HADDRM[31:0]

Output

This is the 32-bit system address bus.

HTRANSM[1:0]

Output

Transfer type. Indicates the type of the current transfer, that can be NONSEQUENTIAL, SEQUENTIAL, or IDLE.

HWRITEM

Output

Transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer.

HSIZEM[2:0]

Output

Transfer size. Indicates the size of the transfer, that can be byte (8-bit), halfword (16-bit), or word (32-bit).

HBURSTM[2:0]

Output

Burst type. This signal indicates if the transfer forms part of a burst. The ARM7TDMI performs incrementing bursts of type INCR.

HPROTM[3:0]

Output

Protection control. These signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a Supervisor mode access or User mode access.

HBUSREQM

Output

Bus request. A signal from the wrapper to the bus arbiter that indicates that it requires the bus.

HLOCKM

Output

Locked transfer. When HIGH, this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

Slave inputs

HTRANS1S

Input

Transfer type. This is attached to bit 1 of the AHB HTRANS[1:0] bus. It indicates an active (NONSEQ or SEQ) or inactive (IDLE or BUSY) transfer.

HWRITES

Input

Transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer.

HWDATAS[31:0]

Input

Write data bus. Used to transfer data to the ARM7TDMI in slave mode.

HSELS

Input

Slave select. Selects the ARM7TDMI as slave.

HREADYS

Input

Transfer done. When HIGH, this signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

Slave outputs

HRDATAS[31:0]

Output

Read data bus. Used to transfer data from the ARM7TDMI in slave mode.

HREADYOUTS

Output

Transfer done. When HIGH, this signal indicates that a transfer to the ARM7TDMI has finished. This signal can be driven LOW to extend a transfer.

HRESPS[1:0]

Output

Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response. The ARM7TDMI always responds with OKAY.

Table 3.2 describes the signals to the ARM7TDMI core.

Table 3.2. Signals to ARM7TDMI core

Signal

Direction

Description

Shared master/slave signals

nRESET

Output

Active LOW reset to core.

MCLK

Output

Core clock for ARM7TDMI.

DIN[31:0]

Output

Data bus. For master mode this is connected to HRDATAM, for test mode it is connected to HWDATAS.

DOUT[31:0]

Input

Data bus. For master mode this is connected to HWDATAM, for test mode it is connected to HRDATAS.

Master inputs

A[31:0]

Input

Address bus

LOCK

Input

Indicates a locked transfer (such as SWP).

MAS[1:0]

Input

Transfer size. Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit).

nMREQ

Input

Not memory access.

nOPC

Input

Not opcode access.

nRW

Input

Not read/write.

nTRANS

Input

Not memory translate. When LOW, this signal indicates that the processor is in user mode.

SEQ

Input

Sequential access.

Master outputs

ABORT

Output

Indicates that an access has aborted (that is, received an ERROR response on the AHB).

nFIQ

Output

Fast interrupt request.

nIRQ

Output

Standard interrupt request.

nWAIT

Output

Indicates that current access is waited.

Test inputs

BUSDIS

Input

Bus disable. When INTEST is selected on scan chain 0, 4, or 8 this is HIGH. It can be used to disable external logic driving onto the bidirectional data bus during scan testing. This signal changes after the falling edge of TCK.

COMMRX

Input

When the communications channel receive buffer is full this is HIGH.

This signal changes after the rising edge of MCLK.

COMMTX

Input

When the communications channel transmit buffer is empty this is HIGH.

This signal changes after the rising edge of MCLK.

DBGACK

Input

Debug acknowledge. When the processor is in a debug state this is HIGH.

DBRQI

Input

Internal debug request. This is the logical OR of DBGRQ and bit 1 of the debug control register.

HIGHZ

Input

When the HIGHZ instruction has been loaded into the TAP controller this signal is HIGH.

RANGEOUT0

Input

EmbeddedICE macrocell. When the EmbeddedICE watchpoint unit 0 has matched the conditions currently present on the address, data, and control buses, then this is HIGH.

This signal is independent of the state of the watchpoint enable control bit.

RANGEOUT1

Input

EmbeddedICE macrocell. As RANGEOUT0 but corresponds to the EmbeddedICE watchpoint unit 1.

nCPI

Input

Not coprocessor instruction. LOW when a coprocessor instruction is processed. The processor then waits for a response from the coprocessor on the CPA and CPB lines.

If CPA is HIGH when MCLK rises after a request has been initiated by the processor, then the coprocessor handshake is aborted, and the processor enters the undefined instruction trap.

If CPA is LOW at this time, the processor enters a busy-wait period until CPB goes LOW before completing the coprocessor handshake.

nENOUT

Input

Not enable output. During a write cycle, this signal is driven LOW before the rising edge of MCLK, and remains LOW for the entire cycle. This can be used to aid arbitration in shared bus applications.

nENOUTI

Input

Not enable output. During a write cycle, this signal is driven LOW before the rising edge of MCLK, and remains LOW for the entire cycle. This can be used to aid arbitration in shared bus applications.

nEXEC

Input

Not executed. This is HIGH when the instruction in the execution unit is not being executed because, for example, it has failed its condition code check.

nM[4:0]

Input

Not processor mode. These are the inverse of the internal status bits indicating the current processor mode.

nTDOEN

Input

Not TDO enable. When serial data is being driven out on TDO this is LOW. Usually used as an output enable for a TDO pin in a packaged part.

SCREG[3:0]

Input

Scan chain register. These reflect the ID number of the scan chain currently selected by the TAP controller. These change on the falling edge of TCK when the TAP state machine is in the UPDATE-DR state.

TBIT

Input

Thumb state. When the processor is executing the THUMB instruction set, this is HIGH. It is LOW when executing the ARM instruction set. This signal changes in phase two in the first execute cycle of a BX instruction.

xnTRST

Input

JTAG reset input from external tester.

xTCK

Input

JTAG clock input from external tester.

xTDI

Input

JTAG data input from external tester.

xTMS

Input

JTAG mode select input from external tester.

xTDO

Input

JTAG data input from core.

Slave outputs

ABE

Output

Address bus enable. The address bus drivers are disabled when this is LOW, putting the address bus into a high impedance state. This also controls the LOCK, MAS[1:0], nRW, nOPC, and nTRANS signals in the same way. ABE must be tied HIGH if there is no system requirement to disable the address drivers.

ALE

Output

Address latch enable. This signal is provided for backwards compatibility with older ARM processors. For new designs, if address retiming is required, ARM Limited recommends the use of APE, and for ALE to be connected HIGH.

The address bus, LOCK, MAS[1:0], nRW, nOPC, and nTRANS signals are latched when this is held LOW. This allows these address signals to be held valid for the complete duration of a memory access cycle. For example, when interfacing to ROM, the address must be valid until after the data has been read.

APE

Output

Address pipeline enable. Selects whether the address bus, LOCK, MAS[1:0], nRW, nTRANS, and nOPC signals operate in pipelined (APE is HIGH) or depipelined mode (APE is LOW).

Pipelined mode is particularly useful for DRAM systems, where it is desirable to provide the address to the memory as early as possible, to allow longer periods for address decoding and the generation of DRAM control signals. In this mode, the address bus does not remain valid to the end of the memory cycle.

Depipelined mode can be useful for SRAM and ROM access. Here the address bus, LOCK, MAS[1:0], nRW, nTRANS, and nOPC signals must be kept stable throughout the complete memory cycle. However, this does not provide optimum performance.

BIGEND

Output

Big-endian configuration. Selects how the processor treats bytes in memory:

HIGH for big‑endian format

LOW for little‑endian format.

BL[3:0]

Output

Byte latch control. The values on the data bus are latched on the falling edge of MCLK when these signals are HIGH. For most designs these signals must be tied HIGH.

BREAKPT

Output

Breakpoint. A conditional request for the processor to enter debug state is made by placing this signal HIGH.

If the memory access at that time is an instruction fetch, the processor enters debug state only if the instruction reaches the execution stage of the pipeline.

If the memory access is for data, the processor enters debug state after the current instruction completes execution. This allows extension of the internal breakpoints provided by the EmbeddedICE Logic.

BUSEN

Output

Bus enable. A static configuration signal that selects whether the bidirectional data bus (D[31:0]) or the unidirectional data buses (DIN[31:0] and DOUT[31:0]) are used for transfer of data between the processor and memory.

When BUSEN is LOW, D[31:0] is used. DOUT[31:0] is driven to a value of zero, and DIN[31:0] is ignored, and must be tied LOW.

When BUSEN is HIGH, DIN[31:0] and DOUT[31:0] are used. D[31:0] is ignored and must be left unconnected.

CPA

Output

Coprocessor absent. Placed LOW by the coprocessor if it is capable of performing the operation requested by the processor.

CPB

Output

Coprocessor busy. Placed LOW by the coprocessor when it is ready to start the operation requested by the processor.

It is sampled by the processor when MCLK goes HIGH in each cycle in which nCPI is LOW.

DBE

Output

Data bus enable. Must be HIGH for data to appear on either the bidirectional or unidirectional data output bus.

When LOW the bidirectional data bus is placed into a high impedance state and data output is prevented on the unidirectional data output bus.

It can be used for test purposes or in shared bus systems.

DBGEN

Output

Debug enable. A static configuration signal that disables the debug features of the processor when held LOW.

This signal must be HIGH to allow the EmbeddedICE Logic to function.

DBGRQ

Output

Debug request. This is a level-sensitive input, that when HIGH causes the ARM7TDMI core to enter debug state after executing the current instruction. This allows external hardware to force the ARM7TDMI core into debug state, in addition to the debugging features provided by the EmbeddedICE Logic.

EXTERN0

Output

External input 0. This is connected to the EmbeddedICE Logic and allows breakpoints and watchpoints to be dependent on an external condition.

EXTERN1

Output

External input 1. This is connected to the EmbeddedICE Logic and allows breakpoints and watchpoints to be dependent on an external condition.

ISYNC

Output

Synchronous interrupts. Set this HIGH if nIRQ and nFIQ are synchronous to the processor clock, LOW for asynchronous interrupts.

nENIN

Output

Not enable input. This must be LOW for the data bus to be driven during write cycles. Can be used in conjunction with nENOUT to control the data bus during write cycles.

nTRST

Output

Not test reset. Reset signal for the boundary-scan logic. This pin must be pulsed or driven LOW to achieve normal device operation, in addition to the normal device reset, nRESET.

SDOUTBS

Output

Boundary scan serial output data. Accepts serial data from an external boundary-scan chain output, synchronized to the rising edge of TCK.

This must be tied LOW, if an external boundary-scan chain is not connected.

TBE

Output

Test bus enable. When LOW, D[31:0], A[31:0], LOCK, MAS[1:0], nRW, nTRANS, and nOPC are set to high impedance.

Similar in effect as if both ABE and DBE had been driven LOW. However, TBE does not have an associated scan cell and so allows external signals to be driven high impedance during scan testing.

Under normal operating conditions TBE must be HIGH.

TCK

Output

Test clock. Clock signal for all test circuitry. When in debug state, this is used to generate DCLK, TCK1, and TCK2.

TDI

Output

Test data in. Serial data for the scan chains.

TMS

Output

Test mode select. Mode select for scan chains.

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