3.3.5. A7WrapSM

In master mode, this block converts the memory accesses from the core into pseudo-AHB accesses. This pseudo-AHB format is similar to AHB-Lite. The following sections of the code are explained:

Main state machine

The main state machine uses the state variable AddrState (which is registered to create LastAddrState). This can take the following enumerated values:

IDLE

Default state. Indicates that no transfer is taking place on the AHB.

IS

Indicates that the current IDLE cycle can be part of a merged I-S access.

NON

Indicates that the current access is a nonsequential transfer.

SEQ

Indicates that the current access is a sequential transfer.

LOKI

Pause state to allow HLOCK to be asserted on the AHB for one cycle prior to the read access of a SWP instruction.

LOKR

Read access of a SWP instruction.

LOKW

Write access of a SWP instruction.

Figure 3.3 shows the possible state transitions. State transitions occur on the rising edge of HCLK. Transitions back to the same state can occur either when the access on the pseudo-AHB is waited, or during sequential accesses in a burst (SEQ only).

Figure 3.3. ARM7 AHB wrapper main state machine

Address generation

There are two internal sources of address:

  • a registered version of the core address

  • a locally incremented address created within A7WrapSM.

Normally the registered version of the address is used, but the registered version is required when performing sequential accesses to prevent a combinational path from the core to HADDR.

Wait states

Wait states on the AHB (indicated by HREADY being LOW) are propagated to the ARM7 only when the core is attempting to access the bus. A string of IDLE cycles will not be waited. Additional wait states (where one wait state equates to a single cycle of HCLK) are added as follows:

  • +1 wait state for each NONSEQ access from the core (except SWP accesses). These are masked by wait states from the previous access, if any are received. Instruction fetches from the ARM7 cores are always initiated as merged I-S cycles, and so do not see this extra wait state.

  • +2 wait states on the read at the start of a SWP instruction. This allows for HLOCK to be asserted for a cycle before the AHB access commences.

Error support

The ARM7 AHB wrappers include support for the ERROR response on HRESP.

Control signaling (HTRANS, HSIZE, HBURST, HPROT)

Table 3.5 shows the control signal values used by the ARM7 AHB wrapper.

Table 3.5. Control signal values

Signal

Value

HTRANS

00: IDLE

10: NONSEQUENTIAL

11: SEQUENTIAL

HSIZE

00: BYTE

01: HALFWORD

10: WORD

HBURST

001: INCR

HPROT

bit 3: (cacheable) 0 for all accesses

bit 2: (bufferable) 0 for all accesses

bit 1: 1 = privileged access, 0 = user access

bit 0: 1 = data access, 0 = opcode fetch

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