3.3.7. A7TWrapTest

The test interface block is used to allow the wrapper module to act as an AHB slave during TIC testing of the core. The main parts of this block are:

The test state machine uses the state variable NextTest (which is registered to create CurrentTest). This can take the following enumerated values:

ST_INACTIVE

Default state. This state is used when the wrapper is not in test mode, and all test outputs are driven to their default levels. The core is clocked as normal in this state.

ST_CTRL_IN

This state is used to load the test register with the control data that is currently on the write data bus. This then determines the values of the control signals that is applied to the core when it is clocked. The core is not clocked during this state.

ST_DATA_IN

In this state write data is being applied to the core (the core is performing a read transfer). The core is clocked in this state.

ST_DATA_OUT

In this state read data is being loaded from the core (the core is performing a write transfer). The core is clocked in this state.

ST_STAT_OUT

This state is used to read the output status signals from the core. The core is not clocked in this state.

ST_ADDR_OUT

This state is used to read the address output from the core. The core is not clocked in this state.

ST_TURNAROUND

This state is used to allow the external data bus time to turnaround between the address read cycle and the control vector write cycle. The core is not clocked in this state.

The state diagram for the test state machine is shown in Figure 3.4.

Figure 3.4. ARM7 AHB wrapper test state machine

The TestEn signal is used to control when test vectors are applied to the core, and controls the transitions through the test state machine. TestEn is set HIGH when the core is addressed during a valid transfer, when the HTRANS input indicates a NONSEQUENTIAL or a SEQUENTIAL transfer.

The 28-bit test register that is loaded during the ST_CTRL_IN state determines the control inputs to the core when it is clocked during the ST_DATA_IN or ST_DATA_OUT states. Table 3.6 shows the control input bit positions.

Table 3.6. ARM7TDMI control input bit position

Signal

Description

Bit position

Comments

SDOUTBS

Boundary scan serial output data

27

-

TBE

Test bus enable

26

-

APE

Address pipeline enable

25

-

BL[3:0]

Byte latch control

24:21

ANDed with TestClk, and should only be valid during data access cycle.

TMS

Test mode select

20

-

TDI

Test data in

19

-

TCK

Test clock

18

ANDed with TestClk.

nTRST

Not test reset

17

-

EXTERN1

External input 1

16

-

EXTERN0

External input 0

15

-

DBGRQ

Debug request

14

-

BREAKPT

Breakpoint

13

-

DBGEN

Debug enable

12

-

ISYNC

Synchronous interrupts

11

-

BIGEND

Big-endian configuration

10

-

CPA

Coprocessor absent

9

-

CPB

Coprocessor busy

8

-

ABE

Address bus enable

7

This must normally be set HIGH, because if the address bus is tristated (ABE LOW), then it is not possible to read address values.

ALE

Address latch enable

6

-

DBE

Data bus enable

5

nFIQ

Not fast interrupt request

4

-

nIRQ

Not interrupt request

3

-

ABORT

Memory abort

2

This must normally be driven when HRESP indicates ERROR, and the wrapper has control of the AHB data bus.

nWAIT

Not wait

1

ANDed with TestClk, so that the core state can only change during the data access cycle.

nRESET

Not reset

0

-

The test data output multiplexor is found in the A7TWrapCtrl block, but is controlled by the test outputs of this block. It is used to select between:

The selected output is driven onto the HRDATAS output data bus.

Table 3.7 shows the bit positions of the status output signals when driven on the data bus.

Table 3.7. ARM7TDMI status bit positions

Signal

Description

Bit position

Comment

BUSDIS

Bus disable

31

-

SCREG[3:0]

Scan chain register

30:27

These signals are not important to the normal functioning of the core, but are included in this test vector to give a slight improvement in fault coverage during scan and debug testing.

HIGHZ

HIGHZ instruction in TAP controller

26

-

nTDOEN

Not TDO enable

25

-

DBGRQ1

Internal debug request

24

-

RANGEOUT0

ICEbreaker Rangeout0

23

-

RANGEOUT1

ICEbreaker Rangeout1

22

-

COMMRX

Communications channel receive

21

-

COMMTX

Communications channel transmit

20

-

DBGACK

Debug acknowledge

19

-

TDO

Test data out

18

This value is often tristate (as indicated by nTDOEN), so is usually masked out.

nENOUT

Not enable output

17

nENOUT is only valid during the data access cycle, so TestClk is used to clock a register that captures the correct state.

nENOUTI

Not enable output

16

nENOUTI is only valid during the data access cycle, so TestClk is used to clock a register that captures the correct state.

TBIT

Thumb state

15

-

nCPI

Not coprocessor instruction

14

-

nM[4:0]

Not processor mode

13:9

-

nTRANS

Not memory translate

8

-

nEXEC

Not executed

7

-

LOCK

Locked operation

6

-

MAS[1:0]

Memory access size

5:4

-

nOPC

Not opcode fetch

3

-

nRW

Not read/write

2

-

nMREQ

Not memory request

1

-

SEQ

Sequential address

0

-

This test interface block can be removed if not required, by removing the A7TWrapTest block from the A7TWrap top level wrapper HDL file. It is then necessary to tie the outputs that were originally generated from this block to fixed values, and these are described in the A7TWrap HDL code.

Removing this block means that the test inputs to the A7TWrapCtrl block is static, allowing the test multiplexors to be removed during synthesis, or manually removed from the HDL code.

The AHB slave outputs are only used during TIC testing mode. HREADYOUTS is always driven HIGH, as the wrapper never generates wait states. HRESPS is always driven to OKAY, as the wrapper never asserts split, retry or error responses.

HRDATAS is generated according to the current test control signal outputs, and is driven to either DOUT from the core, TestData from the test block (which is comprised of the core control outputs), or LOW.

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