3.4.1. Clock gating

A clock inverter is instantiated within A7TWrap (instance name nHCLKgen) to provide nHCLK (inverted HCLK). This signal is used in the following places:

A7TWrap

Creation of dCLKEN, one of the enable terms for MCLK.

A7TWrapTest

Creation of TestModeF, the other enable term for MCLK.

An inverted version of the clock is used so that all HDL code describes only rising-edge sequential logic. This is done because some cell libraries do not contain falling-edge registers, and also to avoid possible insertion of unwanted clock gating during synthesis.

A clock NAND gate is used within A7TWrap (instance name MCLKgen) to create MCLK, the clock for the memory interface of the ARM7TDMI.

The clock gates are described in the design block ClockInv and ClockNand. The methodology chosen within the supplied synthesis scripts synthesizes these blocks first, sets them as dont_touch, and then links them in when synthesizing the wrapper. This ensures that the clock gate instances have known references, and also prevents the optimization routines during later synthesis from altering the gates.

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