AHB Example AMBA SYstem Technical Reference Manual

Table of Contents

About this document
Intended audience
Typographical conventions
Further reading
ARM publications
Other publications
Feedback on this document
Feedback on the AHB Example AMBA SYstem
Timing diagram conventions
1. Introduction
1.1. Overview of EASY
1.1.1. EASY system blocks
1.1.2. EASY components
2. The EASY Microcontroller
2.1. Functional overview
2.2. The AMBA system components
2.2.1. Reset controller
2.2.2. Arbiter
2.2.3. Decoder
2.2.4. AHB to APB bridge
2.3. Reference peripherals
2.3.1. Timer
2.3.2. Interrupt controller
2.3.3. Remap and pause controller
2.4. Example components
2.4.1. Internal memory
2.4.2. Static memory interface
2.4.3. Retry slave
2.4.4. Default slave
2.5. System test methodology
3. ARM7TDMI AHB Wrapper
3.1. About the ARM7TDMI AHB wrapper
3.2. Signal interface
3.3. ARM7TDMI AHB signal descriptions
3.4. Overview of the ARM7TDMI wrapper
3.5. Connections to ARM7TDMI core
3.6. Default signal configurations
3.7. Description of the ARM7TDMI wrapper blocks
3.7.1. A7TWrap
3.7.2. A7TWrapBurst
3.7.3. A7TWrapLock
3.7.4. A7TWrapMaster
3.7.5. A7TWrapCtrl
3.7.6. A7TWrapTest
3.7.7. Non-standard design practices
4. AHB Modules
4.1. APB bridge
4.1.1. Signal descriptions
4.1.2. Peripheral memory map
4.1.3. Function and operation of module
4.1.4. System description
4.2. Arbiter
4.2.1. Signal descriptions
4.2.2. Function and operation of arbiter module
4.2.3. System description
4.3. Decoder
4.3.1. Signal description
4.3.2. System memory map
4.3.3. Function and operation of the decoder module
4.3.4. System description
4.4. Default slave
4.4.1. Signal descriptions
4.4.2. Function and operation of module
4.4.3. System description
4.5. Master to slave multiplexor
4.5.1. Signal descriptions
4.5.2. Function and operation of module
4.5.3. System description
4.6. Slave to master multiplexor
4.6.1. Signal descriptions
4.6.2. Function and operation of module
4.6.3. System description
4.7. Reset controller
4.7.1. Signal descriptions
4.7.2. Function and operation of module
4.7.3. System description
4.8. Retry slave
4.8.1. Signal descriptions
4.8.2. Function and operation of module
4.8.3. System description
4.9. Static memory interface
4.9.1. Signal descriptions
4.9.2. Functional description of the SMI
4.9.3. System description
4.10. Test interface controller
4.10.1. Signal descriptions
4.10.2. Function and operation of module
4.10.3. Test vector sequences
4.10.4. System description
5. APB Modules
5.1. Interrupt controller
5.1.1. Hardware interface and signal description
5.1.2. Function and operation of the interrupt controller module
5.1.3. Register memory map
5.1.4. Register descriptions
5.1.5. Standard configuration of registers
5.1.6. System description
5.2. Remap and pause controller
5.2.1. Signal descriptions
5.2.2. Functions and operations of the remap and pause module
5.2.3. Register memory map
5.2.4. Remap and pause register descriptions
5.2.5. System description
5.3. Timers
5.3.1. Signal descriptions
5.3.2. Function and operation of module
5.3.3. Timer operation
5.3.4. Register memory map
5.3.5. Timer register descriptions
5.3.6. System description
5.3.7. Timer system description
5.3.8. FRC system description
5.3.9. FRC signal descriptions
5.4. Peripheral to bridge multiplexor
5.4.1. Signal descriptions
5.4.2. Function and operation of module
5.4.3. System description
6. Behavioral Modules
6.1. External RAM
6.1.1. Signal descriptions
6.1.2. User-defined settings
6.1.3. Function and operation of module
6.2. External ROM
6.2.1. Signal descriptions
6.2.2. User-defined settings
6.2.3. Function and operation of module
6.3. Internal RAM
6.3.1. AHB signal descriptions
6.3.2. User-defined settings
6.3.3. Function and operation of module
6.4. Test interface driver
6.4.1. Signal descriptions
6.4.2. User-defined settings
6.4.3. Function and operation of module
6.4.4. TICTalk command language
6.4.5. TICTalk commands
6.4.6. Programming with TICTalk commands
6.4.7. The TICTalk file
6.4.8. Generating a test input format file
6.4.9. TIF format file
6.4.10. SIM format file
6.5. Tube
6.5.1. Signal descriptions
6.5.2. User-defined settings
6.5.3. Function and operation of module
7. Designer’s Guide
7.1. Adding bus masters
7.1.1. Arbiter modifications
7.1.2. Bus master requirements
7.2. Adding AHB slaves
7.2.1. AHB slave modifications
7.2.2. Slave requirements
7.3. Adding APB peripherals
7.3.1. APB bridge modifications
7.3.2. Peripheral requirements

List of Figures

1. Key to timing diagram conventions
1.1. EASY system diagram
2.1. Block diagram of the RPS block and bridge
2.2. Simple test veneer example
3.1. ARM7TDMI AHB AMBA wrapper block diagram
3.2. ARM7TDMI AHB wrapper block diagram
3.3. A7TWrapBurst block system diagram
3.4. Address selection state machine
3.5. Address output latches used with slow core output address
3.6. Instruction fetch state machine
3.7. A7TWrapLock block system diagram
3.8. Locked state machine
3.9. A7TWrapMaster block system diagram
3.10. A7TWrapMaster block state machine
3.11. A7TWrapCtrl block system diagram
3.12. A7TWrapTest block system diagram
3.13. A7TWrap Test block state machine
4.1. Block diagram of bridge module
4.2. Peripheral memory map
4.3. State machine for AHB to APB interface
4.4. APB bridge module block diagram
4.5. APB bridge module system diagram
4.6. Arbiter block diagram
4.7. Arbiter module block diagram
4.8. Arbiter module system diagram
4.9. Locked state machine
4.10. Decoder module interface diagram
4.11. System memory map
4.12. Decoder module block diagram
4.13. Decoder module system diagram
4.14. Default slave module interface diagram
4.15. Default slave module block diagram
4.16. Default slave module system diagram
4.17. Master to slave multiplexor module interface diagram
4.18. Master to slave multiplexor module block diagram
4.19. Master to slave multiplexor module system diagram
4.20. Slave to master multiplexor module interface diagram
4.21. Slave to master multiplexor module block diagram
4.22. Slave to master multiplexor module system diagram
4.23. Reset controller module interface diagram
4.24. Reset signal timing
4.25. State machine for reset controller
4.26. Reset controller module block diagram
4.27. Reset controller module system diagram
4.28. Retry slave block diagram
4.29. Retry slave module block diagram
4.30. Retry slave module system diagram
4.31. Static memory interface block diagram
4.32. Zero wait memory read
4.33. Memory write with two wait states
4.34. Static memory interface module block diagram
4.35. Static memory interface module system diagram
4.36. TIC module interface diagram
4.37. Test start sequence
4.38. Write test vectors
4.39. Read test vectors
4.40. Control vector
4.41. Read vector followed by write vector
4.42. TIC module block diagram
4.43. TIC module system diagram
4.44. TIC module granted state machine
4.45. TIC vector state machine
5.1. Interrupt controller module block diagram
5.2. Single bit slice of the interrupt controller
5.3. Interrupt controller module block diagram
5.4. Interrupt controller slice system diagram
5.5. Interrupt controller module system diagram
5.6. Remap and pause module block diagram
5.7. Remap and pause module block diagram
5.8. Remap and pause module system diagram
5.9. Pause signal timing
5.10. Timer module block diagram
5.11. Timer operation
5.12. Prescale clock enable generation
5.13. The control register
5.14. Timers module block diagram
5.15. Timers module system diagram
5.16. Timer module counter enable timing - system clock selected
5.17. Timer module counter enable timing - test clock selected
5.18. FRC module block diagram
5.19. FRC module system diagram
5.20. FRC module count down diagram
5.21. Peripheral to bridge multiplexor module interface diagram
5.22. Peripheral to bridge multiplexor module block diagram
5.23. Peripheral to bridge multiplexor module system diagram
6.1. External RAM module interface diagram
6.2. External ROM module interface diagram
6.3. AHB internal RAM module interface diagram
6.4. Ticbox module interface diagram
6.5. Tube module interface diagram

List of Tables

2.1. Peripherals base addresses
3.1. ARM7TDMI AHB signal descriptions
3.2. Connections of ARM7TDMI signals
3.3. ARM7TDMI control input bit position
3.4. ARM7TDMI status bit positions
4.1. Signal descriptions for bridge module
4.2. Signal descriptions
4.3. Decoder module signal descriptions
4.4. Default slave module signal descriptions
4.5. Master to slave multiplexor signal descriptions
4.6. Slave to master multiplexor signal descriptions
4.7. Reset controller signal descriptions
4.8. Signal descriptions
4.9. Memory map of the example AHB retry slave
4.10. Signal descriptions
4.11. XCSN coding
4.12. XWEN coding
4.13. TIC signal descriptions for AHB
4.14. Test control signals during normal operation
4.15. Test control signals during test mode
4.16. Control vector bit definitions
5.1. APB signal descriptions for interrupt controller
5.2. Register memory map of the interrupt controller APB peripheral
5.3. Example of IRQ sources
5.4. APB signal descriptions for remap and pause controller
5.5. Memory map of the remap and pause controller APB peripheral
5.6. APB signal descriptions for timer
5.7. Memory map of the time APB peripheral
5.8. Test register bit functions
5.9. Signal descriptions for FRC
5.10. Signal descriptions for peripheral to bridge multiplexor module
6.1. Signal descriptions for the external RAM module
6.2. User-defined settings for the external RAM module
6.3. Signal descriptions for the external ROM module
6.4. User-defined settings for the external ROM module
6.5. Signal descriptions for the AHB internal RAM module
6.6. User-defined settings for the external RAM module
6.7. Signal descriptions for the Ticbox module
6.8. User-defined settings for the Ticbox module
6.9. Signal descriptions for the tube module
6.10. User-defined settings for the tube module
6.11. Valid tube ASCII control characters
6.12. Commonly used ASCII alphanumeric characters

Proprietary Notice

ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of ARM Limited.

The ARM logo, AMBA, PrimeCell, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, TDMI and STRONG are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AAugust 1999First release
Copyright © 1999 ARM Limited. All rights reserved.DDI0170A