3.3.4. Command register, MCICommand

The MCICommand register contains the command index and command type bits:

The command index is sent to a card as part of a command message
The command type bits control the Command Path State Machine (CPSM). Writing 1 to the enable bit starts the command send operation, while clearing the bit disables the CPSM.

Table 3.5 shows the bit assignment of the MCICommand register.

Table 3.5. MCICommand register

Bit	Name	Type	Function
5:0	CmdIndex	Read/write	Command index
6	Response	Read/write	If set, CPSM waits for a response
7	LongRsp	Read/write	If set, CPSM receives a 136-bit long response
8	Interrupt	Read/write	If set, CPSM disables command timer and waits for interrupt request
9	Pending	Read/write	If set, CPSM waits for CmdPend before it starts sending a command
10	Enable	Read/write	If set, CPSM is enabled
31:11	Reserved	-	-

After a data write, data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods.

Table 3.6 shows the response types.

Table 3.6. Command response types

Response	LongRsp.	Description
0	0	No response, expect CmdSent flag
0	1	No response, expect CmdSent flag
1	0	Short response, expect CmdRespEnd or CmdCrcFail flag
1	1	Long response, expect CmdRespEnd or CmdCrcFail flag

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