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The PrimeCell MCI test registers are memory-mapped as shown in Table 4.1.
Table 4.1. Test registers memory map
Address | Type | Width | Reset value | Name | Description |
|---|---|---|---|---|---|
MCIBase + | Read/write | 4 |
| MCITCR | Test control register |
MCIBase + | Read/write | 6/1 |
| MCIITIP | Integration test input register |
MCIBase + | Read/write | 12 |
| MCIITOP | Integration test output register |
Each register shown in Table 4.1 is described below.
| Copyright © 1998 ARM Limited. All rights reserved. | ARM DDI0172A |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model for Test > Test registers |