SC054 ASB Technical Reference Manual 3.3.1. Bank configuration registers SMCBCR0-7

3.3.1. Bank configuration registers SMCBCR0-7

The descriptions of the bits for the bank configuration registers are given in Table 3.3.

Table 3.3. SMCBCR 0 - 7 register definition

Bits	Name	Type	Description
31-30	AT	Read/write	Reserved, do not modify, unpredictable when read.
29-28	MW	Read/write	Memory width:^[1] 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = reserved.
27	BM	Read/write	Burst mode: 0 = nonburst devices (default at reset) 1 = burst ROM.
26	WP	Read/write	Write protect: 0 = SRAM, not write protected (default at reset) 1 = ROM, burst ROM and SRAM are write-protected.
25	WPERR	Read/write	Write protect error status flag, read: 0 = no error (default at reset) 1 = write protect error. Writing a 1 to this bit clears the write protect error status flag.
24	BUSERR	Read/write	Bus transfer error status flag, read: 0 = no error (default at reset) 1 = bus transfer error. Writing a 1 to this bit clears the bus transfer error status flag.
23	CSPol	Read/write	Chip select polarity bit indication for each bank: 0 = active LOW CS (default at reset) 1 = active HIGH CS.
22	WaitEn	Read/write	External memory controller wait signal enable: 0 = the SC054 ASB SMC is not controlled by the external wait signal (default at reset) 1 = the SC054 ASB SMC looks for the external wait input signal, SMnWAIT.
21	WaitPol	Read/write	Polarity of the external wait input for activation: 0 = the SMnWAIT signal is active LOW (default at reset) 1 = the SMnWAIT signal is active HIGH.
20-16	-	-	Reserved, do not modify, unpredictable when read.
15-11	WST2	Read/write	Wait state 2. Defaults to 11111 at reset. SRAM, the WST2 field controls the number of wait states for write accesses. This wait state time is (WST2 + 1) x tBCLK in the case of SRAM. Burst ROM, the WST2 field controls the number of wait states for the burst read accesses after the first read. This wait state time is (WST2) x tBCLK in the case of burst ROM. ROM: WST2 does not apply to ROM devices.
10	RBLE	Read/write	Read byte lane enable. Defaults to 0 at reset. 0 = SMnBLS[3:0] all deasserted HIGH during system reads from external memory. 1 = SMnBLS[3:0] all asserted LOW during system reads from external memory.
9-5	WST1	Read/write	Wait state 1. Defaults to 11111 at reset. SRAM and ROM, the WST1 field controls the number of wait states for read accesses. Burst ROM, the WST1 field controls the number of wait states for the first read access only. Wait state time = (WST1 + 1) x tBCLK.
4	-	-	Reserved, do not modify, unpredictable when read.
3-0	IDCY	Read/write	Idle or turnaround cycles. Defaults to 11111 at reset. This field controls the number of bus turnaround cycles added between read and write accesses, to prevent bus contention on the external memory data bus. The turn around time is (IDCY + 1) x tBCLK.
^[1] In the SC054 ASB SMC, the MW field defaults to 16-bit width for all memory banks at reset, (see Table 3.4).

Table 3.4. SC054 ASB SMC reset default memory width

SMC memory bank	Default memory width
Bank 0	16-bit
Bank 1	16-bit
Bank 2	16-bit
Bank 3	16-bit
Bank 4	16-bit
Bank 5	16-bit
Bank 6	16-bit
Bank 7	16-bit

At reset the memory bank default external memory width is as shown in Table 3.4.

Note

If the system boots from a Bank0 external ROM device that is not 16-bit wide, you must amend the VHDL RTL code and the C verification test program to configure the correct default external memory width at reset.

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