TestMode

Input

Test interface controller

Test mode input.

This signal indicates the test controller has taken control of the bus. When HIGH, this signal enables the External Bus Interface (EBI) for the 32-bit test bus. It also selects TCLK as the system clock source.

Ticinen

Input

Test interface controller

Test data in enable input.

This active LOW signal indicates that the SC054 ASB SMC should drive the SMDATIN (TBUS) into the BD. Must be tied HIGH when not connected to the TIC.

Ticouten

Input

Test interface controller

Test data out enable input.

This active LOW signal indicates that the SC054 ASB SMC must drive its latched version of BD onto the external SMDATAOUT (TBUS). Must be tied HIGH when not connected to the TIC.

TicoutLen

Input

Test interface controller

Test data out latch enable input.

BD latch enable for the data bus in the external memory bus. When LOW the BD latch should be transparent. Must be tied HIGH when not connected to the TIC.

BIGENDIAN

Input

System

This static configuration bit indicates the type of endianness of the memory system:

1 = big-endian

0 = little-endian.

SCANMODE

Input

Scan test controller

Scan test mode input.

This signal must be asserted HIGH during scan testing to ensure that bidirectional tristate signals are tristated and not driven. SCANENABLE must be deasserted LOW during normal use or when applying TicTalk test vectors through the TIC macro block.

SCANENABLE

Input

Scan test controller

Scan test enable input.

This signal must be driven during scan testing to control the input multiplexors of scan flip-flops. SCANENABLE must be deasserted LOW during normal use or when applying TicTalk test vectors through the TIC macro block.

This signal is not functionally connected within the peripheral. It is a dummy pin that is used during the scan insertion process.

SCANINBCLK

Input

Scan test logic

Dedicated scan chain input for flip-flops clocked by BCLK.

This signal is not functionally connected within the peripheral. It is a dummy pin that is used during the scan insertion process.

SCANINnBCLK

Input

Scan test logic

Dedicated scan chain input for flip-flops clocked by nBCLK.

This signal is not functionally connected within the peripheral. It is a dummy pin that is used during the scan insertion process.

SCANOUTBCLK

Input

Scan test logic

Dedicated scan chain output for flip-flops clocked by BCLK.

This signal is not functionally connected within the peripheral. It is a dummy pin that is used during the scan insertion process.

SCANOUTnBCLK

Input

Scan test logic

Dedicated scan chain output for flip-flops clocked by nBCLK.

This signal is not functionally connected within the peripheral. It is a dummy pin that is used during the scan insertion process.

SMBUSREQ

Output

EBI

When asserted HIGH, SMBUSREQ requests access to EBI.

SMBUSGNT

Input

EBI

When asserted HIGH, SMBUSGNT indicates that the slave is granted the EBI.

SMDATAIN[31:0]

Input

Input/output pad

External data input bus. Data read from external memory.

Input

Input/output pad

Wait mode input from external memory controller. Active HIGH or active LOW activation as programmed in the SMC configuration registers for each bank.

SMDATAOUT[31:0]

Output

Input/output pad

External data output bus. Data is written to external memory.

SMADDR[22:0]

Output

Input/output pad

External address bus to off-chip memory.

SMnDATAEN[3:0]

Output

Input/output pad

Tristate input/output pad enables to control the byte lanes of the external data output bus SMDATAOUT, active LOW. The SMnDATAEN signals 0 to 3, independently control SMDATAOUT signals 0 to 7, 8 to15, 16 to 23, and 24 to 31 respectively. The SMnDATAEN signals are connected to the appropriate SMDATAOUT input/output pad enables and asserted LOW to drive data out on the data pads.

SMnCS[7:0]

Output

Input/output pad

Chip select for external memory banks 0 to 7, active LOW or active HIGH programmable by configuring the CS polarity for each bank independently.

SMnOEN

Output

Input/output pad

Output enable for external memory banks, active LOW.

SMnWEN

Output

Input/output pad

Write enable for the external memory banks, active LOW.

SMnBLS[3:0]

Output

Input/output pad

Byte lane select signals, active LOW. The signals SMnBLS[3:0] select byte lanes [31:24], [23:16], [15:8], and [7:0] on external memory devices.