You must configure each bank of the SC054 ASB SMC for wait states in read and write accesses. This is achieved by programming the appropriate fields of the bank configuration registers SMCBCRx.

Wait state control refers to external transfer wait states. The number of cycles in which an AMBA transfer completes is controlled by two other factors:

You can program the WST1 wait state field to select from 1 to 32 wait states for read memory accesses to SRAM and ROM, or the initial burst read access to burst ROM.

You can program the WST2 wait state field to select from 0 to 32 wait states for write access to SRAM or 0 to 31 wait states in the case of burst mode reads from Burst ROM devices. For example, the configuration for an access to a burst ROM with a 120ns initial access time followed by a 60ns burst access time, using a 150MHz system clock is 18 wait states for the first access and 9 for the subsequent accesses.

The SC054 ASB SMC can also be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses. The IDCY field can be programmed for 1 to 16 bus turnaround wait cycles. This is to avoid bus contention on the external memory data bus.

Figure 2.2 illustrates a single bus turnaround cycle added before a write access that follows a read access.

After the read transfer completes successfully, read data is driven onto BD[31:0] and a DONE response is given. BA and BWRITE then change immediately. As the next transaction is a write, there is a one cycle turnaround to avoid possible external bus contention. Data is then transferred from BD to SMDATAOUT.