The SC054 ASB SMC has the same type of read timing control for ROM, SRAM, and FLASH devices. Each read starts with the assertion of the appropriate memory bank chip select signals SMnCS[x] and memory address SMADDR[22:0]. The read access time is determined by the number of wait states programmed for the WST1 field of the bank configuration register SMCBCRx. The IDCY field in the bank configuration register determines the number of bus turnaround wait cycles added between external read and write transfers.

Figure 2.3 shows an external memory read transfer with the minimum one WAIT state (WST1 = 0).

Figure 2.4 shows an external memory read transfer with two WAIT states (WST1 = 1).

The SC054 ASB SMC supports sequential access burst reads of up to four consecutive locations in 8, 16, or 32-bit memories. This feature supports burst mode ROM devices and increases the bandwidth by using a reduced (configurable) access time for three sequential reads following a quad-location boundary read.

For the burst ROM the property of slower initial access (as programmed in the WST1 register) and subsequent faster access (as programmed in the WST2 register) is exploited. The WST2 for the subsequent access is used until the quad boundary for the memory device is reached. The quad boundary for different memory device sizes are indicated in the note under question.

For example, if the first access is to boundary for a byte wide device, which occurs when BA[1:0] = 11, then it means that the quad location boundary is already reached. The next read access is done again with the longer access time as in WST1. The subsequent read accesses then use the faster access time as in WST2 until the quad location is reached.

Figure 2.5 shows an external memory burst read transfer, using 2 initial WAIT states and 0 WAIT cycles for the subsequent burst read accesses. The transfer size is 32 bits wide, but the memory is only byte wide. Therefore, in this case a word is built up from four byte reads.