The SC054 ASB SMC generates byte lane write control signals SMnBLS[3:0] according to:

Table 2.4 shows the basic coding assuming 32-bit external memory.

Both big-endian and little-endian operations are supported as defined by a dedicated input signal to the SC054 ASB SMC.

Word transfers are the largest sized transfers supported by the SC054 ASB SMC. Any access attempted with a size greater than a word is treated as invalid and causes the error response to be generated.

Figure 2.8 shows typical connections for a little-endian memory system with different data width memory devices.

If the device is a byte partioned device with the memory constructed using 16-bit, or 32-bit devices, this is indicated by programming the RBLE = 1 in the configuration register. In this case both the SMnWEN and SMnBLS signals are used. The SMnWEN gates the SMnBLS lines.

If the device is a nonbyte partioned device with the memory constructed using only 8-bit devices, this is indicated by programming RBLE = 0. Here the SMnWEN line is not used and only SMnBLS lines are used as write enables for the memory device.