To ensure low-power operation, the transitions on the external address bus are kept to a minimum by enabling the address bus transitions only during memory accesses.

The data out path allows 32-bit AMBA writes to be converted into several external memory halfword or byte writes. The separate byte lane write signals ensure that the entire memory bus is driven at all times, no matter what width of memory is being accessed. The data in path constructs 32-bit ASB data words from halfword and byte wide external static memory devices. For buses less than 32-bits wide unused bits are automatically driven by the SC054 ASB SMC. Devices are always connected from bit 0 upwards for both little and big-endian configurations.

The SMBUSREQ signal is driven HIGH when external bus access is required. After the SMBUSGNT signal is received the SC054 ASB SMC starts driving address and data information on the next cycle. The SC054 ASB SMC keeps the SMBUSREQ signal HIGH as long as it requires the bus. Once the external transaction is completed SMBUSREQ is driven LOW. Figure 2.9 shows when SMBUSGNT is given immediate access to the bus, and Figure 2.10 shows when the access is delayed for two cycles because another memory controller is accessing the bus.

When the EBRI is not required the SC054 ASB SMC supports the use of its external memory data bus as the bidirectional test port (TBUS) for the AMBA TIC. The system allows testing by application of parallel TicTalk test vectors through the external bus interface to test AMBA blocks by creating bus transfers on the AMBA ASB and AMBA APB buses. For systems using less than 32-bit external data width, other device pins (for example the address pins) must have special test functionality to provide a 32-bit test data width, connecting bidirectional pads that can act as inputs during system test.