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Table A.3. Coprocessor interface signals
Name | Direction | Description |
|---|---|---|
CHSD[1:0] | Input | Coprocessor Handshake Decode. The handshake signals from the decode stage of the coprocessors pipeline follower. Note, if no coprocessor is present in the system, CHSD[1] should be tied HIGH, and CHSD[0] should be tied LOW. |
CHSE[1:0] | Input | Coprocessor Handshake Execute. The handshake signals from the execute stage of the coprocessors pipeline follower. Note, if no coprocessor is present in the system, CHSE[1] should be tied HIGH, and CHSE[0] should be tied LOW. |
LATECANCEL | Output | Coprocessor Late Cancel. If HIGH during the first memory cycle of a coprocessor instruction’s execution, the coprocessor should cancel the instruction without having updated its state. |
PASS | Output | Coprocessor PASS. This signal indicates that there is a coprocessor instruction in the execute stage of the pipeline, and it should be executed. |
For further information on the coprocessor interface refer to Chapter 4 ARM9TDMI Coprocessor Interface.