The ARM9TDMI supports 32-bit, 16-bit and 8-bit data memory access sizes. The endian configuration of the processor, set by BIGEND, affects only non-word transfers (16‑bit and 8-bit transfers).

For data writes by the processor, the write data is duplicated on the data bus. So for a 16-bit data store, one copy of the data appears on the upper half of the data bus, DD[31:16], and the same data appears on the lower half, DD[15:0]. For 8-bit writes four copies are output, one on each byte lane, DD[31:24], DD[23:16], DD[15:8] and DD[7:0]. This considerably eases the memory control logic design and helps overcome any endian effects.

For data reads, the processor will read a specific part of the data bus. This is determined by the endian configuration, the size of the transfer, and bits 1 and 0 of the data address bus. Table 3.5 shows which bits of the data bus are read for 16-bit reads, and Table 3.6 shows which bits are read for 8-bit reads.

For simplicity of design, 32 bits of data can be read from memory and the processor will ignore any unwanted bits.