Whenever an instruction enters the execute stage of the pipeline, a new opcode is fetched from the instruction bus. The ARM9TDMI processor core may be connected to a variety of cache/SRAM systems, and it is optimized for single cycle access systems.

However, in order to ease the system design, it is possible to connect the ARM9TDMI to memory which takes two (or more) cycles for a non-sequential (N) access, and one cycle for a sequential (S) access. Although this increases the effective CPI, it considerably eases the memory design.

The ARM9TDMI indicates that an instruction fetch will take place by driving InMREQ LOW. The instruction address bus, IA[31:1] will contain the address for the fetch, and the ISEQ signal will indicate whether the fetch is sequential or non‑sequential to the previous access. All these signals become valid towards the end of phase 2 of the cycle that precedes the instruction fetch.

If ITBIT is LOW, and thus ARM9TDMI is performing word reads, then IA[1] should be ignored.

The timing is shown in Figure 3.2. The full encoding of InMREQ and ISEQ is as follows:

Instruction fetches may be marked as aborted. The IABORT signal is an input to the processor with the same timing as the instruction data. If, and when, the instruction reaches the execute stage of the pipeline, the prefetch abort vector is taken. The timing for this is shown in Figure 3.2. If the memory control logic does not make use of the IABORT signal, it must be tied LOW.

Internal cycles occur when the processor is stalled, either waiting for an interlock to resolve, or completing a multi-cycle instruction.

Figure 3.2 shows the cycle timing for an N followed by an S cycle, where there is a prefetch abort on the S cycle: