When nRESET is driven LOW, the currently executing instruction terminates abnormally. If GCLK is HIGH, InMREQ, ISEQ, DnMREQ, DSEQ and DMORE will asynchronously change to indicate an internal cycle. If GCLK is LOW, they will not change until after the GCLK goes HIGH.

When nRESET is driven HIGH, the ARM9TDMI starts requesting memory again once the signal has been synchronized, and the first memory access will start two cycles later. The nRESET signal is sampled on the falling edge of GCLK. The behavior of the memory interfaces coming out of reset is shown in Figure 3.4.