Any instruction being fetched for memory is latched at the end of phase 2. To apply a breakpoint to that instruction, the breakpoint signal must be asserted by the end of the following phase1. This minimizes the setup time, giving the EmbeddedICE macrocell an entire phase in which to perform the comparison. This is shown in Figure 5.2.

External logic, such as additional breakpoint comparators, may be built to extend the functionality of the EmbeddedICE macrocell. Their output should be applied to the IEBKPT input. This signal is simply ORed with the internally generated Breakpoint signal before being applied to the ARM9TDMI core control logic.

A breakpointed instruction is allowed to enter the execute stage of the pipeline, but any state change as a result of the instruction is prevented. All writes from previous instructions complete as normal.

The decode cycle of the debug entry sequence occurs during the execute cycle of the breakpointed instruction. The latched Breakpoint signal forces the processor to start the debug sequence.