ARM9TDMI™ Technical Reference Manual 5.16.1. Debug comms channel registers

5.16.1. Debug comms channel registers

The debug comms control register is read only, and allows synchronized handshaking between the processor and the debugger.

Figure 5.15. Debug comms control register

The function of each register bit is described below:

Bits 31:28: Contain a fixed pattern that denotes the EmbeddedICE macrocell version number, in this case 0010.
Bits 27:2: Unused.
Bit 1: Denotes from the processor’s point of view, whether the comms data write register is free. If, from the processor’s point of view, the comms data write register is free (W=0), new data may be written. If it is not free (W=1), the processor must poll until W=0. If, from the debugger’s point of view, W=1, some new data has been written which may then be scanned out.
Bit 0: Denotes whether there is some new data in the comms data read register. If, from the processor’s point of view, R=1, there is some new data which may be read via an MRC instruction. If, from the debugger’s point of view, R=0, the comms data read register is free and new data may be placed there through the scan chain. If R=1, this denotes that data previously placed there through the scan chain has not been collected by the processor, and so the debugger must wait.

From the debugger’s point of view, the registers are accessed via the scan chain in the usual way. From the processor, these registers are accessed via coprocessor register transfer instructions. The following instructions should be used:

MRC p14, 0, Rd, c0, c0, 0

Returns the debug comms control register into Rd.

MCR p14, 0, Rn, c1, c0, 0

Writes the value in Rn to the comms data write register.

MRC p14, 0, Rd, c1, c0, 0

Returns the debug data read register into Rd.

Note

The Thumb instruction set does not support coprocessors so the ARM9TDMI must be operated in ARM state in order to access the debug comms channel.

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