In the fourth example, the following code sequence is executed:

LDM R12,{R1-R3}

ADD R4, R3, R1

The code is the same code as in example 3, but in this instance the ADD instruction uses R3. Due to the nature of load multiples, the lowest register specified is transferred first, and the highest specified register last. Because the ADD is dependent on R3, there must be a further cycle of interlock while R3 is loaded. The behavior on the instruction and data memory interface is shown in Figure 7.4.