The coprocessor is permitted to stall, or busy-wait, the processor during the execution of a coprocessor instruction if, for example, it is still busy with an earlier coprocessor instruction. To do so, the coprocessor associated with the decode stage instruction drives WAIT onto CHSD[1:0]. When the instruction concerned enters the execute stage of the pipeline the coprocessor may drive WAIT onto CHSE[1:0] for as many cycles as necessary to keep the instruction in the busy-wait loop.

For interrupt latency reasons the coprocessor may be interrupted while busy-waiting, thus causing the instruction to be abandoned. Abandoning execution is done through PASS. The coprocessor must monitor the stage of PASS during every busy-wait cycle.

If it is HIGH, the instruction should still be executed. If it is LOW, the instruction should be abandoned. Figure 4.7 shows a busy-waited coprocessor instruction being abandoned due to an interrupt: