ARM9TDMI ™ TechnicalReference Manual

(Rev 3)

Table of Contents

About this manual
Intended audience
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the ARM9TDMI
1.2. Processor block diagram
2. Programmer’s Model
2.1. About the programmer’s model
2.1.1. Data abort model
2.1.2. Instruction set extension spaces
2.2. Pipeline implementation and interlocks
3. ARM9TDMI Processor Core Memory Interface
3.1. About the memory interface
3.1.1. Actions of the ARM9TDMI in debug state
3.1.2. Wait states
3.2. Instruction interface
3.3. Endian effects for instruction fetches
3.4. Data interface
3.5. Unidirectional/bidirectional modeinterface
3.6. Endian effects for data transfers
3.7. ARM9TDMI reset behavior
4. ARM9TDMI Coprocessor Interface
4.1. About the coprocessor interface
4.2. LDC/STC
4.2.1. Coprocessor handshake encoding
4.3. MCR/MRC
4.4. Interlocked MCR
4.5. CDP
4.6. Privileged instructions
4.7. Busy-waiting and interrupts
4.8. Coprocessor 15 MCRs
5. Debug Support
5.1. About debug
5.2. Debug systems
5.2.1. The debug host
5.2.2. The protocol converter
5.2.3. The ARM9TDMI
5.3. Debug interface signals
5.3.1. Entry into debug state on breakpoint
5.3.2. Breakpoints and exceptions
5.3.3. Watchpoints
5.3.4. Watchpoints and exceptions
5.3.5. Debug request
5.3.6. Actions of the ARM9TDMI in debug state
5.4. Scan chains and JTAG interface
5.5. The JTAG state machine
5.5.1. Reset
5.5.2. Pullup resistors
5.5.3. Instruction register
5.5.4. Public instructions
5.6. Test data registers
5.6.1. Bypass register
5.6.2. ARM9TDMI device identification (ID)code register
5.6.3. Instruction register
5.6.4. Scan chain select register
5.6.5. Scan chains 0, 1, 2, and 3
5.7. ARM9TDMI core clocks
5.8. Clock switching during debug
5.9. Clock switching during test
5.10. Determining the core state and systemstate
5.10.1. Determining the core state
5.10.2. Determining system state
5.10.3. Instructions which may have the SYSSPEED bit set
5.11. Exit from debug state
5.12. The behavior of the program counterduring debug
5.12.1. Breakpoint
5.12.2. Watchpoint
5.12.3. Watchpoint with another exception
5.12.4. Watchpoint and breakpoint
5.12.5. Debug request
5.12.6. System speed accesses
5.12.7. Summary of return address calculations
5.13. EmbeddedICE macrocell
5.13.1. Register map
5.13.2. Using the mask registers
5.13.3. Control registers
5.13.4. Debug control register
5.13.5. Debug status register
5.13.6. Vector catch register
5.14. Vector catching
5.15. Single stepping
5.16. Debug communications channel
5.16.1. Debug comms channel registers
5.16.2. Communications via the comms channel
6. Test Issues
6.1. About testing
6.2. Scan chain 0 bit order
7. Instruction Cycle Summary and Interlocks
7.1. Instruction cycle times
7.1.1. Multiplier cycle counts
7.2. Interlocks
7.2.1. Example 1
7.2.2. Example 2
7.2.3. Example 3
7.2.4. Example 4
8. ARM9TDMI AC Characteristics
8.1. ARM9TDMI timing diagrams
8.2. ARM9TDMI timing parameters
A. ARM9TDMI Signal Descriptions
A.1. Instruction memory interface signals
A.2. Data memory interface signals
A.3. Coprocessor interface signals
A.4. JTAG and TAP controller signals
A.5. Debug signals
A.6. Miscellaneous signals

List of Figures

1. Key to timing diagram conventions
1.1. ARM9TDMI processor block diagram
2.1. ARM9TDMI processor core instruction pipeline
3.1. ARM9TDMI clock stalling using nWAIT
3.2. Instruction fetch timing
3.3. Data access timings
3.4. ARM9TDMI reset behavior
4.1. ARM9TDMI LDC / STC cycle timing
4.2. ARM9TDMI coprocessor clocking
4.3. ARM9TDMI MCR / MRC transfer timing
4.4. ARM9TDMI interlocked MCR
4.5. ARM9TDMI late cancelled CDP
4.6. ARM9TDMI privileged instructions
4.7. ARM9TDMI busy waiting and interrupts
4.8. ARM9TDMI coprocessor 15 MCRs
5.1. Typical debug system
5.2. Breakpoint timing
5.3. Watchpoint entry with data processinginstruction
5.4. Watchpoint entry with branch
5.5. Test access port (TAP) controllerstate transitions
5.6. Clock switching on entry to debug state
5.7. Debug exit sequence
5.8. Debug state entry
5.9. ARM9TDMI EmbeddedICE macrocell overview
5.10. Watchpoint control register for datacomparison
5.11. Watchpoint control register for instructioncomparison
5.12. Debug control register
5.13. Debug status register
5.14. Vector catch register
5.15. Debug comms control register
7.1. Single load interlock timing
7.2. Two cycle load interlock
7.3. LDM interlock
7.4. LDM dependent interlock
8.1. ARM9TDMI instruction memory interface output timing
8.2. ARM9TDMI instruction address bus enable
8.3. ARM9TDMI instruction memory interface input timing
8.4. ARM9TDMI data memory interface output timing
8.5. ARM9TDMI data address bus timing
8.6. ARM9TDMI data ABORT and DnMREQ timing
8.7. ARM9TDMI data data bus timing
8.8. ARM9TDMI data bus enable
8.9. ARM9TDMI miscellaneous signal timing
8.10. ARM9TDMI coprocessor interface signal timing
8.11. ARM9TDMI JTAG output signals
8.12. ARM9TDMI external boundary scan chain output signals
8.13. ARM9TDMI SDOUTBS to TDO relationship
8.14. ARM9TDMI nTRST to RSTCLKBS relationship
8.15. ARM9TDMI JTAG input signal timing
8.16. ARM9TDMI GCLK related debug output timings
8.17. ARM9TDMI TCK related debug output timings
8.18. ARM9TDMI nTRST to DBGRQI relationship
8.19. ARM9TDMI EDBGRQ to DBGRQI relationship
8.20. ARM9TDMI DBGEN to output effects

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A March2000 First release
Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0180A