4.3.3. Integration Test Output Registers

The read-only VICITOP1 Register, with address offset of 0x30C, is a 32-bit register that controls the nVICIRQ and nVICFIQ outputs. Figure 4.3 shows the bit assignments for this register.

Figure 4.3. VICITOP1 Register bit assignments

Table 4.5 lists the bit assignments for this register.

Table 4.5. VICITOP1 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined.

[7]

VICIRQ

Reads return the value on the internal VICIRQ line. This is the pre-inverted version of the final output, and is inverted to create the final nVICIRQ output.

[6]

VICFIQ

Reads return the value on the internal VICFIQ line. This is the pre-inverted version of the final output, and is inverted to create the final nVICFIQ output.

[5:0]

-Read undefined.

The read-only VICITOP2 Register, with address offset of 0x310, is a 32-bit register that controls the VICVECTADDROUT output. Table 4.6 lists the bit assignments for this register.

Table 4.6. VICITOP2 Register bit assignments

Bits

Name

Description

[31:0]

VICVECTADDROUT

Reads return the value on the VICVECTADDROUT lines.

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