3.4.1. FIQ interrupts

FIQ interrupts have the highest priority in the VIC, and are not nested. In FIQ mode, seven 32-bit registers are banked into the system. This enables the VIC to process the interrupt as quickly as possible. Table 3.23 lists the worst case cycles for FIQ interrupts.

Table 3.23. FIQ interrupt latency

Event

Worst case (cycles)

Interrupt synchronization.

3

Worst case instruction execution. This assumes that a standard switch reduces STM and LDM. You can reduce this to 7 cycles to avoid data aborts.

7

Entry to first instruction.

2

Total.

12

Note

For the best results, start the FIQ handler at the FIQ vector address, 0x1c.

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