PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference ManualRevision: r1p2
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3.3.2. FIQ Status Register

The read-only VICFIQSTATUS Register, with address offset of 0x004, provides the status of the interrupts after FIQ masking. Table 3.3 lists the bit assignments for this register.

Table 3.3. VICFIQSTATUS Register bit assignments

Bits

Name

Function

[31:0]

FIQStatus

Shows the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers. A HIGH bit indicates that the interrupt is active, and generates an interrupt to the processor.

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