PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference ManualRevision: r1p2
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3.3.10. Vector Address Register

The read/write VICVECTADDR Register, with address offset of 0x030, contains the Interrupt Service Routine (ISR) address of the currently active interrupt. Table 3.11 lists the bit assignments for this register.

Table 3.11. VICVECTADDR Register bit assignments

Bits

Name

Function

[31:0]

VectorAddr

Contains the address of the currently active ISR. Any writes to this register clear the interrupt.

Note

Reading from this register provides the address of the ISR, and indicates to the priority hardware that the interrupt is being serviced. Writing to this register indicates to the priority hardware that the interrupt has been serviced. You must use this register as follows:

  • the ISR reads the VICVectAddr Register when an IRQ interrupt is generated

  • at the end of the ISR, the VICVectAddr Register is written to, to update the priority hardware.

Reading from or writing to the register at other times can cause incorrect operation.

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