3.3.13. Vector Control Registers

The read/write VICVECTCNTL[0-15] Registers span address locations 0x200-0x23C and select the interrupt source for the vectored interrupt. Figure 3.2 shows the bit assignments for these registers.

Figure 3.2. VICVECTCNTL Register bit assignments

Table 3.14 lists the bit assignments for these registers.

Table 3.14. VICVECTCNTL Registers bit assignments

Bits

Name

Function

[31:6]

-

Read undefined. Write as zero.

[5]

E

Enables vector interrupt. This bit is cleared on reset.

[4:0]

IntSource

Selects interrupt source. You can select any of the 32 interrupt sources.

Note

Vectored interrupts are only generated if the interrupt is enabled. The specific interrupt is enabled in the VICIntEnable Register, and the interrupt is set to generate an IRQ interrupt in the VICIntSelect Register. This prevents multiple interrupts being generated from a single request if the controller is incorrectly programmed.

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