3.3.3. Raw Interrupt Status Register

The read-only VICRAWINTR Register, with address offset of 0x008, provides the status of the source interrupts, and software interrupts, to the interrupt controller. Table 3.4 lists the bit assignments for this register.

Table 3.4. VICRAWINTR Register bit assignments

Bits

Name

Function

[31:0]

RawInterrupt

Shows the status of the interrupts before masking by the enable registers. A HIGH bit indicates that the appropriate interrupt request is active before masking.

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