Because of the additional read required to read both the primary VICVectAddr Register and the daisy-chained VICVectAddr Register, the worst-case latency of the primary VIC increases by one cycle, to 26 cycles. The worst-case latency for the secondary, daisy-chained VIC increases by two cycles, to 27 cycles. This latency applies to any number of secondary VICs. See Daisy-chained vectored interrupt service routine for more information.