PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference ManualRevision: r1p2
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3.3.11. Default Vector Address Register

The read/write VICDEFVECTADDR Register, with address offset of 0x034, contains the default ISR address. Table 3.12 lists the bit assignments for this register

Table 3.12. VICDEFVECTADDR Register bit assignments

Bits

Name

Function

[31:0]

Default VectorAddr

Contains the address of the default ISR handler

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