3.3.14. Peripheral Identification Registers

The read-only VICPeriphID0-3 Registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. You can treat the registers conceptually as a single 32-bit register. The read-only registers provide the following options for the peripheral:

Part number [11:0]

This identifies the peripheral. The VIC uses the three-digit product code 0x90.

Designer [19:12]

This is the identification of the designer. ARM Limited is 0x41, ASCII A.

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.3 shows the bit assignments for these registers.

Figure 3.3. Peripheral Identification Register bit allocation

The following sections describe the four 8-bit Peripheral Identification Registers:

VICPERIPHID0 Register

The read-only VICPERIPHID0 Register, with address offset of 0xFE0, is hard-coded, and the fields within the register determine the reset value. Figure 3.4 shows the bit assignments for this register.

Figure 3.4. VICPERIPHID0 Register bit assignments

Table 3.15 lists the bit assignments for this register.

Table 3.15. VICPERIPHID0 Register bit assignments

Bits

Name

Function

[31:8]

-

Read undefined

[7:0]

Partnumber0

These bits read back as 0x90

VICPERIPHID1 Register

The read-only VICPERIPHID1 Register, with address offset of 0xFE4, is hard-coded, and the fields within the register determine the reset value. Figure 3.5 shows the bit assignments for this register.

Figure 3.5. VICPERIPHID1 Register bit assignments

Table 3.16 lists the bit assignments for this register.

Table 3.16. VICPERIPHID1 Register bit assignments

Bits

Name

Function

[31:8]

-

Read undefined

[7:4]

Designer0

These bits read back as 0x1

[3:0]

Partnumber1

These bits read back as 0x1

VICPERIPHID2 Register

The read-only VICPERIPHID2 Register, with address offset of 0xFE8, is hard-coded and the fields within the register determine the reset value. Figure 3.6 shows the bit assignments for this register.

Figure 3.6. VICPERIPHID2 Register bit assignments

Table 3.17 lists the bit assignments for this register.

Table 3.17. VICPERIPHID2 Register bit assignments

Bits

Name

Function

[31:8]

-

Read undefined

[7:4]

Revision

These bits read back as 0x1

[3:0]

Designer1

These bits read back as 0x0

VICPERIPHID3 Register

The read-only VICPERIPHID3 Register, with address offset of 0xFEC., is hard-coded and the fields within the register determine the reset value. Figure 3.7 shows the bit assignments for this register.

Figure 3.7. VICPERIPHID3 Register bit assignments

Table 3.18 lists the bit assignments for this register.

Table 3.18. VICPERIPHID3 Register bit assignments

Bits

Name

Function

[31:8]

-

Read undefined

[7:0]

Configuration

These bits read back as 0x0

Copyright © 2000, 2003-2004 ARM Limited. All rights reserved.ARM DDI 0181E
Non-Confidential