PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference Manual 3.3.15. PrimeCell Identification Registers

3.3.15. PrimeCell Identification Registers

The read-only VICPCELLID0-3 Registers are four 8-bit registers that span address locations 0xFF0-0xFFC. You can treat them conceptually as a single 32-bit register. Use the register as a standard cross-peripheral identification system. Figure 3.8 shows the bit assignment for these registers.

Figure 3.8. PrimeCell Identification Register bit assignment

The four 8-bit registers are described in the following subsections:

VICPCELLID0 Register

The read-only VICPCELLID0 Register, with address offset of 0xFF0, is hard-coded and the fields within the register determine the reset value. Figure 3.9 shows the bit assignments for this register.

Figure 3.9. VICPCELLID0 Register bit assignments

Table 3.19 lists the bit assignments for this register.

Table 3.19. VICPCELLID0 Register bit assignments

Bits	Name	Function
[31:8]	-	Read undefined
[7:0]	VICPCellID0	These bits read back as `0x0D`

VICPCELLID1 Register

The read-only VICPCELLID1 Register, with address offset of 0xFF4, is hard-coded and the fields within the register determine the reset value. Figure 3.10 shows the bit assignments for this register.

Figure 3.10. VICPCELLID1 Register bit assignments

Table 3.20 lists the bit assignments for this register.

Table 3.20. VICPCELLID1 Register bit assignments

Bits	Name	Function
[31:8]	-	Read undefined
[7:0]	VICPCellID1	These bits read back as `0xF0`

VICPCELLID2 Register

The read-only VICPCELLID2 Register, with address offset of 0xFF8, is hard-coded and the fields within the register determine the reset value. Figure 3.11 shows the bit assignments for this register.

Figure 3.11. VICPCELLID2 Register bit assignments

Table 3.21 lists the bit assignments for this register.

Table 3.21. VICPCELLID2 Register bit assignments

Bits	Name	Function
[31:8]	-	Read undefined
[7:0]	VICPCellID2	These bits read back as `0x05`

VICPCELLID3 Register

The read-only VICPCELLID3 Register, with address offset of 0xFFC, is hard-coded and the fields within the register determine the reset value. Figure 3.12 shows the bit assignments for this register.

Figure 3.12. VICPCELLID3 Register bit assignments

Table 3.22 lists the bit assignments for this register.

Table 3.22. VICPCELLID3 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Read undefined
[7:0]	VICPCellID3	RO	These bits read back as `0xB1`

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