3.4.2. IRQ interrupts

In IRQ mode, you can nest interrupt levels lower than the highest priority FIQ interrupt level. To provide this nesting, the return address, stored in the Link Register (LR), and the status register, stored in the Saved Processor Status Register (SPSR) must be available before more IRQ interrupts can be accepted. This increases the interrupt latency, but provides a scalable nested interrupt system. Table 3.24 lists the worst case cycles for IRQ interrupts.

Table 3.24. IRQ interrupt latency

Event

Worst case (cycles)

Interrupt synchronization

3

Worst case interrupt disable period

10

Entry to first instruction

2

Nesting, assuming single-state AHB

10

Total

25

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