PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference ManualRevision: r1p2
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3.3.12. Vector Address Registers

The read/write VICVECTADDR[0-15] Registers span address locations 0x100-0x13C and contain the ISR vector addresses. Table 3.13 lists the bit assignments for these registers.

Table 3.13. VICVECTADDR Registers bit assignments

Bits

Name

Function

[31:0]

VectorAddr 0-15

Contains ISR vector addresses

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