3.5. Interrupt priority

The hardware regulates the interrupt priority. FIQ interrupts have the highest priority, followed by vectored interrupt 0 to vectored interrupt 15. Non-vectored interrupts have the lowest priority.

To reduce interrupt latency, you can re-enable the IRQ interrupts in the processor after the Interrupt Service Routine (ISR) is entered. See Interrupt latency. In this case, the current ISR is interrupted, and the higher-priority ISR is executed. The VIC then only enables a higher priority interrupt than the interrupt currently being serviced. If a higher priority interrupt goes active, the current ISR is interrupted and the higher-priority ISR is executed.

Before the interrupt enable bits in the processor can be re-enabled, the LR and SPSR must be saved, preferably on a software stack. When the ISR is exited, you must disable the interrupts, reload the LR and SPSR, and write to the Vector Address Register, VICVectAddr. See Vectored interrupt service routine.

When you daisy-chain VICs, the interrupt priority is as follows:

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