PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference Manual 3.3.5. Interrupt Enable Register

3.3.5. Interrupt Enable Register

The read/write VICINTENABLE Register, with address offset of 0x010, enables the interrupt request lines, by masking the interrupt sources for the IRQ interrupt. Table 3.6 lists the bit assignments for this register.

Table 3.6. VICINTENABLE Register bit assignments

Bits	Name	Function
[31:0]	IntEnable	Enables the interrupt request lines: 1 = Interrupt enabled. Enables interrupt request to processor. 0 = Interrupt disabled. On reset, all interrupts are disabled. A HIGH bit sets the corresponding bit in the VICINTENABLE Register. A LOW bit has no effect.

Bits

Name

Function

[31:0]

IntEnable

Enables the interrupt request lines:

1 = Interrupt enabled. Enables interrupt request to processor.

0 = Interrupt disabled.

On reset, all interrupts are disabled. A HIGH bit sets the corresponding bit in the VICINTENABLE Register. A LOW bit has no effect.

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