2.2.1. Vectored interrupt flow sequence

The following procedure shows the sequence for the vectored interrupt flow:

  1. An interrupt occurs.

  2. The ARM processor branches to either the IRQ or FIQ interrupt vector.

  3. If the interrupt is an IRQ, read the VICVectAddr Register and branch to the interrupt service routine. You can do this using an LDR PC instruction. Reading the VICVectorAddr Register updates the interrupt controllers hardware priority register.

  4. Stack the workspace so that you can re-enable IRQ interrupts.

  5. Enable the IRQ interrupts so that a higher priority can be serviced.

  6. Execute the Interrupt Service Routine (ISR).

  7. Clear the requesting interrupt in the peripheral, or write to the VICSoftIntClear Register if the request was generated by a software interrupt.

  8. Disable the interrupts and restore the workspace.

  9. Write to the VICVectAddr Register. This clears the respective interrupt in the internal interrupt priority hardware.

  10. Return from the interrupt. This re-enables the interrupts.

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