You normally use the VIC as a standalone interrupt controller.
Where required, you can daisy-chain a second VIC.
The VIC connects to the processor as a standard AHB slave,
with the FIQ and IRQ signals connected to the FIQ and IRQ inputs
on the processor. The interrupt request lines from the peripheral
connect to the VICINTSOURCE inputs
of the VIC. To ensure that you can read the vector address register
in a single instruction, you must put the VIC in the upper 4K of
memory, at 0xFFFFF000. See Vector Address Register.
Note
If the VIC is located at a different address, interrupt latency
increases.
The following sections describe the connectivity for the two
options:
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