2.1. About the VIC

The VIC provides a software interface to the interrupt system. In a system with an interrupt controller, software must determine the source that is requesting service and where its service routine is loaded. A VIC does both of these in hardware. It supplies the starting address, or vector address, of the service routine corresponding to the highest priority requesting interrupt source.

In an ARM system, two levels of interrupt are available:

Fast Interrupt reQuest (FIQ)

For fast, low latency interrupt handling.

Interrupt ReQuest (IRQ)

For more general interrupts.

Generally, you only use a single FIQ source at a time in a system to provide a true low-latency interrupt. This has the following benefits:

The interrupt inputs must be level sensitive, active HIGH, and held asserted until the interrupt service routine clears the interrupt. Edge-triggered interrupts are not compatible.

The interrupt inputs do not have to be synchronous to HCLK.

Note

The VIC does not handle interrupt sources with transient behavior. For example, an interrupt is asserted and then deasserted before software can clear the interrupt source. In this case, the CPU acknowledges the interrupt and obtains the vectored address for the interrupt from the VIC, assuming that no other interrupt has occurred to overwrite the vectored address. However, when a transient interrupt occurs, the priority logic of the VIC is not set, and lower priority interrupts can interrupt the transient interrupt service routine, assuming interrupt nesting is permitted.

There are 32 interrupt lines. The VIC uses a bit position for each different interrupt source. The software can control each request line to generate software interrupts.

There are 16 vectored interrupts. These interrupts can only generate an IRQ interrupt. The vectored and non-vectored IRQ interrupts provide an address for an Interrupt Service Routine (ISR). Reading from the Vector Interrupt Address Register, VICVECTADDR, provides the address of the ISR, and updates the interrupt priority hardware that masks out the current, and any lower priority interrupt requests. Writing to the VICVECTADDR Register indicates to the interrupt priority hardware that the current interrupt is serviced, enabling lower priority or the same priority interrupts to be removed, and for the interrupts to become active to go active.

The FIQ interrupt has the highest priority, followed by interrupt vector 0 to interrupt vector 15. Non-vectored IRQ interrupts have the lowest priority. A programmed interrupt request enables you to generate an interrupt under software control. This register typically downgrades an FIQ interrupt to an IRQ interrupt.

Note

  • The ARM core sets the priority of the FIQ over IRQ.

  • The VIC can raise both an FIQ and an IRQ at the same time.

The IRQ and FIQ request logic has an asynchronous path to the nVICIRQ and nVICFIQ outputs respectively. This enables you to assert interrupts when the VIC AHB clock, HCLK, is disabled in a low-power mode. It is expected that the power control logic enables the processor and VIC AHB clocks when an interrupt is received, so that the interrupt service routine can be performed.

By convention, for the IRQ interrupt, you are recommended to use bits 1 to 5 that Table 2.1 defines. Bit 0 and bit 6 upwards are available for you to use. For the FIQ interrupt, you can use all the bits.

Table 2.1. Recommended interrupt standard configuration

Bit

Interrupt source

1

Software interrupt

2

Comms Rx

3

Comms Tx

4

Timer 1

5

Timer 2

A space is reserved for the software interrupt so that you can use it without masking out a valid hardware interrupt. You can program any of the interrupt bits through software using the VICSOFTINT Register but, by reserving a specific software interrupt bit, it is easier to differentiate between hardware and software interrupts.

The Comms RX and TX lines are debug channel interrupts that the system processor uses, and they are required in any system that uses these debug features.

Spaces are reserved for two timers because a typical system has at least two timers.

Figure 2.1 shows a block diagram of the VIC.

Figure 2.1. VIC block diagram

The following sections describe the main components of the VIC:

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