3.1. About the programmer’s model

To ensure that you can read the vector address register in a single instruction, the VIC base address must be 0xFFFFF000, that is the upper 4K of memory. See Vector Address Register. Placing the VIC anywhere else in memory increases interrupt latency because the ARM processor cannot access the VICVectorAddr Register using a single instruction.

The read, LDR, instruction has a maximum address offset of 12 bits, equivalent to 4K, meaning that it can read from an address up to 4K away from the current address with a single read instruction. If the address to be read from is more than 4K away, you require a second instruction to read in the full address value. This takes longer to perform.When an interrupt occurs, the current address is either the IRQ or FIQ exception vector location, 0x00000018 or 0x0000001C for normal low exception vectors. A 4K offset from the exception address is the upper 4K of memory, so placing the VIC in this area of memory enables the read of the VICADDRESS Register, at 0xFFFFFF00, to be performed using an address offset with a single instruction. For example, at location 0x18 LDR pc, [pc, #-0x120] to access VICADDRESS at location 0xFFFFFF00.

If you use a processor that supports high exception vectors, and you tie the HIVECS configuration pin HIGH, you must put the VIC at 0xFFFEF000 to enable the exception vectors that are located at 0xFFFFF000. The VIC is not located at 0x00000000, because this is the standard location for the system memory. The offset of any particular register from the base address is fixed.

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