PrimeCell® Vectored Interrupt Controller (PL190) Technical Reference Manual 4.3. Summary of test registers

PrimeCell^® Vectored Interrupt Controller (PL190) Technical Reference Manual

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4.3. Summary of test registers

Table 4.1 lists how the VIC test registers are memory-mapped.

Table 4.1. Test registers memory map

Register	Address offset	Type	Reset value	Description
VICITCR	`0x300`	R/W	`-`	See Test Control Register
VICITIP1	`0x304`	RO	`0x0`	See Integration Test Input Registers
VICITIP2	`0x308`	RO	`-`	See Integration Test Input Registers
VICITOP1	`0x30C`	RO	`0x0`	See Integration Test Output Registers
VICITOP2	`0x310`	RO	`0x00000000`	See Integration Test Output Registers

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