3.3.1. IRQ Status Register

The read-only VICIRQSTATUS Register, with address offset of 0x000, provides the status of interrupts [31:0] after IRQ masking. Table 3.2 lists the bit assignments for this register.

Table 3.2. VICIRQSTATUS Register bit assignments

Bits

Name

Function

[31:0]

IRQStatus

Shows the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers. A HIGH bit indicates that the interrupt is active, and generates an interrupt to the processor.

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