4.3.2. Integration Test Input Registers

The read-only VICITIP1 Register, with address offset of 0x304, is a 2-bit register that returns the values of the nVICIRQIN and nVICFIQIN inputs. Figure 4.2 shows the bit assignments for this register.

Figure 4.2. VICITIP1 Register bit assignments

Table 4.3 lists the bit assignments for this register.

Table 4.3. VICITIP1 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7]

nVICIRQIN

Reads return the value on nVICIRQIN when the VICITCR Register is LOW

[6]

nVICFIQIN

Reads return the value on nVICFIQIN when the VICITCR Register is LOW

[5:0]

-

Read undefined

The VICITIP2 Register, with address offset of 0x308, is a read-only register. It is a 32-bit register that returns the value of the VICVECTADDRIN input. Table 4.4 lists the bit assignments for this register.

Table 4.4. VICITIP2 Register bit assignments

Bits

Name

Description

[31:0]

VICVECTADDRIN

Reads return the value on VICVECTADDRIN when the VICITCR Register is LOW.

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