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| Home > Functional Overview > About the VIC > Vectored interrupts |
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A vectored interrupt is only generated if the following are true:
you enable it in the interrupt enable register, VICIntEnable
you set it to generate an IRQ interrupt in the interrupt select register, VICIntSelect
you enable it in the relevant vector control register, VICVectCntl[0-15].
This prevents multiple interrupts being generated from a single interrupt request if the controller is incorrectly programmed.
| Copyright © 2000, 2003-2004 ARM Limited. All rights reserved. | ARM DDI 0181E |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > About the VIC > Vectored interrupts |