PrimeCell ® VectoredInterrupt Controller (PL190) Technical Reference Manual

Revision: r1p2

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the VIC
1.1.1. Features of the VIC
1.2. Product revisions
2. Functional Overview
2.1. About the VIC
2.1.1. Interrupt request logic
2.1.2. Non-vectored FIQ interrupt logic
2.1.3. Non-vectored IRQ interrupt logic
2.1.4. Vectored interrupt block
2.1.5. Interrupt priority logic
2.1.6. Vectored interrupts
2.1.7. Software interrupts
2.2. Operation
2.2.1. Vectored interrupt flow sequence
2.2.2. Simple interrupt flow
2.3. Connectivity
2.3.1. Standalone interrupt controller
2.3.2. Daisy-chained interrupt controller
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of VIC registers
3.3. Register descriptions
3.3.1. IRQ Status Register
3.3.2. FIQ Status Register
3.3.3. Raw Interrupt Status Register
3.3.4. Interrupt Select Register
3.3.5. Interrupt Enable Register
3.3.6. Interrupt Enable Clear Register
3.3.7. Software Interrupt Register
3.3.8. Software Interrupt Clear Register
3.3.9. Protection Enable Register
3.3.10. Vector Address Register
3.3.11. Default Vector Address Register
3.3.12. Vector Address Registers
3.3.13. Vector Control Registers
3.3.14. Peripheral Identification Registers
3.3.15. PrimeCell Identification Registers
3.4. Interrupt latency
3.4.1. FIQ interrupts
3.4.2. IRQ interrupts
3.4.3. Fast IRQ interrupts
3.4.4. Daisy-chained interrupts
3.5. Interrupt priority
4. Programmer’s Model for Test
4.1. VIC test harness overview
4.2. Scan testing
4.3. Summary of test registers
4.3.1. Test Control Register
4.3.2. Integration Test Input Registers
4.3.3. Integration Test OutputRegisters
A. Signal Descriptions
A.1. AMBA AHB signals
A.2. Interrupt controller signals
A.3. Daisy-chain signals
A.4. Scan test control signals
B. Example Code
B.1. About the example code
B.1.1. Enable interrupts
B.1.2. Disable interrupts
B.1.3. Interrupt polling
B.1.4. Generate software interrupt
B.1.5. Clear software interrupt
B.1.6. FIQ interrupt initialization
B.1.7. FIQ interrupt handler
B.1.8. Simple interrupt initialization
B.1.9. Simple interrupt service routine
B.1.10. Vectored interrupt initialization
B.1.11. Vectored interrupt service routine
B.1.12. Daisy-chained vectored interrupt serviceroutine
B.1.13. Highest level vectored IRQ interruptservice routine

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 30June 2000 First release
Revision B August2000 Small corrections to code examples
Revision C September2000 VICITIP1 & 2 changed to read-only. Changesto Figs 2-5 & 2-6
Revision D 02July 2003 Incorporate errata, revision r1p1
Revision E 30November 2004 Incorporate erratum, revision r1p2
Copyright © 2000, 2003-2004 ARM Limited. All rights reserved. ARM DDI 0181E