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| Home > Programmer’s Model > Register descriptions > PrimeCell identification registers, UARTPCellID0-3 |
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The UARTPCellID0-3registers are four 8-bit wide registers,
that span address locations 0xFF0-0xFFC.
The registers can conceptually be treated as a 32-bit register.
The register is used as a standard cross-peripheral identification
system. The UARTPCellID register is set to 0xB105F00D. Figure 3.2 shows the bit assignment
for the UARTPCellID0-3 registers.
The four, 8-bit PrimeCell identification registers are described in the following subsections:
The UARTPCellID0 register is hard coded and the fields within the register determine the reset value. Table 3.23 shows the bit assignment of the UARTPCellID0 register.
The UARTPCellID1 register is hard coded and the fields within the register determine the reset value. Table 3.24 shows the bit assignment of the UARTPCellID1 register.
The UARTPCellID2 register is hard coded and the fields within the register determine the reset value. Table 3.25 shows the bit assignment of the UARTPCellID2 register.
The UARTPCellID3 register is hard coded and the fields within the register determine the reset value. Table 3.26 shows the bit assignment of the UARTPCellID3 register.
| Copyright © 2000, 2001, 2005 ARM Limited. All rights reserved. | ARM DDI 0183F |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Register descriptions > PrimeCell identification registers, UARTPCellID0-3 |