PrimeCell ® UART(PL011) Technical Reference Manual

Revision: r1p5

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Additional reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the UART
1.1.1. Features
1.1.2. Programmable parameters
1.1.3. Variations from the 16C650 UART
1.2. Product revisions
2. Functional Overview
2.1. Overview
2.1.1. IrDA SIR block
2.2. Functional description
2.2.1. AMBA APB interface
2.2.2. Register block
2.2.3. Baud rate generator
2.2.4. Transmit FIFO
2.2.5. Receive FIFO
2.2.6. Transmit logic
2.2.7. Receive logic
2.2.8. Interrupt generation logic
2.2.9. DMA interface
2.2.10. Synchronizing registers and logic
2.2.11. Test registers and logic
2.3. IrDA SIR ENDEC functional description
2.3.1. IrDA SIR transmit encoder
2.3.2. IrDA SIR receive decoder
2.4. Operation
2.4.1. Interface reset
2.4.2. Clock signals
2.4.3. UART operation
2.4.4. IrDA SIR operation
2.4.5. UART character frame
2.4.6. IrDA data modulation
2.5. UART modem operation
2.6. UART hardware flow control
2.6.1. RTS flow control
2.6.2. CTS flow control
2.7. UART DMA interface
2.8. Interrupts
3. Programmers Model
3.1. About the programmers model
3.2. Summary of registers
3.3. Register descriptions
3.3.1. Data Register, UARTDR
3.3.2. Receive Status Register / Error ClearRegister, UARTRSR/UARTECR
3.3.3. Flag Register, UARTFR
3.3.4. IrDA Low-Power Counter Register, UARTILPR
3.3.5. Integer Baud Rate Register, UARTIBRD
3.3.6. Fractional Baud Rate Register, UARTFBRD
3.3.7. Line Control Register, UARTLCR_H
3.3.8. Control Register, UARTCR
3.3.9. Interrupt FIFO Level Select Register,UARTIFLS
3.3.10. Interrupt Mask Set/Clear Register, UARTIMSC
3.3.11. Raw Interrupt Status Register, UARTRIS
3.3.12. Masked Interrupt Status Register, UARTMIS
3.3.13. Interrupt Clear Register, UARTICR
3.3.14. DMA Control Register, UARTDMACR
3.3.15. Peripheral Identification Registers,UARTPeriphID0-3
3.3.16. PrimeCell Identification Registers,UARTPCellID0-3
4. Programmers Model for Test
4.1. Test harness overview
4.2. Scan testing
4.3. Summary of test registers
4.4. Test register descriptions
4.4.1. Test Control Register, UARTTCR
4.4.2. Integration Test Input Register, UARTITIP
4.4.3. Integration Test Output Register,UARTITOP
4.4.4. Test Data Register, UARTTDR
4.5. Integration testing of block inputs
4.5.1. Intra-chip inputs
4.5.2. Primary inputs
4.6. Integration testing of block outputs
4.6.1. Intra-chip outputs
4.6.2. Primary outputs
4.7. Integration test summary
A. Signal Descriptions
A.1. AMBA APB signals
A.2. On-chip signals
A.3. Signals to pads

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 12July 2000 First release.
Revision B 18August 2000 Change to signal names in Fig 2-1,changes to bits in Figs 4-1, 4-3.
Revision C 9February 2001 Change to Figure 2-7. Note addedto para 3.3.6.
Revision D 15February 2001 Text change to pages 2-9, and 2-12.
Revision E 14December 2001 Text changes to pages 3-13, 3-14,and 3-17.
Revision F 01November 2005 Update to add Errata 01, historyof product revision, fix for defect 326409.
Revision G 18December 2007 Update for r1p5. Text changes to Clocksignals on page 2‑10 and UARTTXINTR on page 2‑23.Buffer depthof the receive and transmit FIFOs increased.
Copyright © 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G